DDR5 RAM Hits $375 Floor for PC Builders: HBM Takes Three Times More Wafers

Anyone planning a new PC build or workstation upgrade in 2026 needs to revise their memory budget: the minimum price for a 32GB DDR5 kit has crossed $375, and the structural reasons behind that floor are unlikely to ease before late 2027 at the earliest. Price tracking via PCPartPicker, reported by Tom's Hardware on June 3, now shows the cheapest available 32GB DDR5 kit at $374.97 — for a Silicon Power Zenith RGB DDR5-6000 kit — with no comparable option available below that level.

A component that cost less than $100 a year ago now costs nearly four times as much. The driver is not a logistics disruption or a manufacturing accident. It is a deliberate capital allocation decision playing out across the global semiconductor industry — and until the industry builds new fabrication capacity, the $375 figure is not a ceiling. It may well be the floor.

AI Hyperscalers Have First Claim on DRAM Wafers

The three companies that collectively control more than 95% of global DRAM production — SK Hynix, Samsung, and Micron — have systematically redirected their manufacturing capacity toward high-bandwidth memory (HBM) for AI data centers.

The economics are straightforward: an HBM module sells for roughly $60 to $100, compared to $5 to $10 for a comparable amount of conventional DDR5 DRAM. When production capacity is constrained and one product category generates margins five to ten times higher than another, rational manufacturers will always prioritize the higher-margin product. Standard consumer DDR5 DIMMs sit at the bottom of that priority queue.

The result is visible in PC parts pricing. A mainstream gaming build targeting 32GB — the current practical floor for modern multitasking, development workflows, or content creation — now carries a memory line-item that can rival a mid-range CPU. Popular branded kits from Corsair and Crucial command more than $400, and top-end 64GB configurations reach $679.99, according to PCPartPicker data reported by Tom's Hardware.

HBM Architecture: Why One AI Memory Chip Devours Three DDR5 Wafers

The key to understanding why building more memory has not solved the shortage lies in how HBM is manufactured — and how radically different that process is from making a standard DDR5 module.

A conventional DDR5 DIMM is built from flat, planar DRAM dies printed on silicon wafers and soldered onto a printed circuit board. The manufacturing process is mature, high-yield, and relatively straightforward. A high-bandwidth memory module is something else entirely.

HBM stacks multiple DRAM dies vertically — typically eight to twelve layers — and connects them with thousands of microscopic copper pathways called through-silicon vias (TSVs). The entire stack is then bonded directly onto a silicon interposer alongside the AI accelerator it serves, using an advanced packaging technique known as Chip-on-Wafer-on-Substrate (CoWoS). Where a standard DDR5 DIMM sends data through a narrow 64-bit channel at high speed, an HBM stack delivers data through a 1,024-bit-wide interface — trading slower per-pin rates for massive parallelism, and achieving bandwidth of up to 1.2 terabytes per second per stack on current HBM3E hardware.

This architecture is why HBM consumes roughly three times the wafer capacity per gigabyte compared to DDR5, according to Tom's Hardware analysis. The vertical stacking process reduces yields; the TSV formation requires additional processing steps; and CoWoS advanced packaging has itself become a major bottleneck, with TSMC's specialized assembly lines running at capacity.

As Samsung entered HBM4 mass production in early 2026, it did so by converting wafer starts from commodity DDR5 lines — removing more consumer DRAM bits from the supply pool than the HBM4 production added back in AI memory bits. TrendForce estimates that one gigabyte of HBM requires the equivalent of four gigabytes of standard DRAM in wafer area. HBM already accounts for roughly 30% of all DRAM revenue despite representing only about 8% of total memory output in bits. That ratio is widening.

Manufacturers Confirm No Near-Term Relief

The executives running the three major DRAM manufacturers have been unusually candid about the timeline.

SK Group chairman Chey Tae-won, at Nvidia's GTC conference in San Jose on March 16, said the memory supply shortfall would persist at over 20% through 2030 and that "securing additional wafers takes at least four to five years." At Computex in Taipei on June 2, he pledged to double SK Hynix's total wafer production capacity within five years — while simultaneously acknowledging that doubling capacity would still not close the demand gap given the trajectory of AI spending. Sources cited by Reuters reported that SK Hynix's available capacity is "essentially zero," with no portion available to designate to specific customers regardless of price or relationship.

Samsung's memory chief Kim Jaejune warned on April 30 that "significant shortages" across memory products are expected through at least 2027. The company's semiconductor division posted $36.1 billion in operating profit during the first quarter of 2026, with soaring AI memory demand accounting for roughly 94% of total quarterly profit.

Gartner, in a February 26 analysis, projected that combined DRAM and SSD prices will surge 130% by year-end 2026, contributing to a 17% year-over-year increase in PC prices and a 10.4% decline in global PC shipments.

New fabrication capacity is under construction but will not deliver meaningful relief within the current shortage window. Samsung's P5 megafab in Pyeongtaek, South Korea, targets mass production in the latter part of 2028. SK Hynix's M15X facility is slated for utilization by mid-2027. Micron, which broke ground on a leading-edge DRAM fab in Boise, Idaho, projects first wafer output in mid-2027.

The US government has added a further risk layer: in January 2026, Commerce Secretary Howard Lutnick threatened 100% tariffs on offshore DRAM production unless manufacturers like SK Hynix and Samsung commit to building memory fabs on American soil. Neither company currently manufactures DRAM dies in the United States — only packaging operations. If those tariffs materialize, they would push consumer memory prices higher still.

nbd-vram: How GPU VRAM Swap Works and When It Helps

Against this backdrop, a small open-source project released on May 31 has caught the attention of the Linux developer community as a practical — if unconventional — pressure valve.

nbd-vram, published by developer c0deJedi, allows Linux users running NVIDIA consumer GPUs to repurpose idle GPU video memory (VRAM) as Linux swap space. The mechanism is specific and worth understanding, because it sidesteps a well-known restriction in NVIDIA's driver stack.

The conventional approach to accessing GPU memory from the CPU is the NVIDIA P2P API, which pins VRAM pages in BAR1 memory so the CPU can reach them directly. NVIDIA's driver blocks this path on consumer GeForce GPUs — the feature is locked to Quadro and datacenter SKUs at the driver level, regardless of driver version. nbd-vram takes a different route entirely.

A small daemon allocates VRAM via the NVIDIA CUDA driver API, then serves that allocated block as a block device using the Network Block Device (NBD) protocol over a Unix socket. The kernel's built-in NBD driver connects to the daemon and exposes /dev/nbdX as a standard swap device. The data path runs from the kernel swap subsystem through the NBD kernel driver, across the Unix socket to the daemon, and then through CUDA memory copy calls into GPU VRAM. No kernel module is required, which means the solution survives driver and kernel updates without rebuilding anything.

The tool was validated on an NVIDIA RTX 3070 laptop, where up to 7 GB of VRAM was successfully allocated as swap, significantly expanding the machine's total addressable memory.

The limitations matter for anyone weighing whether this is useful. Data written to GPU VRAM swap must traverse the PCIe bus, which introduces substantially higher latency than accessing system DRAM directly. GPU VRAM is also fast memory attached to a fast processor — occupying it with swap data means those resources cannot be simultaneously used for GPU workloads. The tool is designed for machines where VRAM is routinely sitting partially idle: Linux laptops with soldered memory and no upgrade path, developer machines running CPU-bound workloads with a GPU mostly idle, or homelab servers where the GPU handles inference tasks intermittently. It is not a substitute for proper DRAM in latency-sensitive workloads, and using it during a GPU-intensive task will negate any memory benefit.

What PC Builders Can Do Now

For anyone planning a new build or upgrade in 2026, the practical guidance is specific. The $375 price floor applies to the minimum-spec 32GB DDR5 kit; popular RGB or high-frequency kits from Corsair, Crucial, or G.Skill run $400 or above. Budget planning that assumed memory costs from 18 months ago will be materially wrong.

One potential sign of future relief: in late May, Corsair DDR5 kits were spotted containing DRAM manufactured by ChangXin Memory Technologies (CXMT), a Chinese memory maker that has been ramping consumer DDR5 production. CXMT, unlike the three dominant memory makers, is not tied to AI data center contracts and has available production lines targeting the consumer market. Its specifications — DDR5-6000 at CL36 timings, 1.35V — are mainstream and perform comparably to Samsung or SK Hynix-based kits in benchmarks. If CXMT supply reaches Western markets at scale, it could introduce downward pricing pressure.

Builders with existing DDR5 systems built in 2024 or early 2025 are best positioned: adding capacity when prices ease will not require a platform change. Those building new systems on Intel or AMD platforms have no alternative to DDR5 — DDR4 support has been sunset on both current-generation platforms. Budget-minded builders willing to start with 16GB and upgrade later may find the interim approach worthwhile.

The long-term structural picture is unchanged: the infrastructure buildout sustaining AI model development at hyperscale has reshuffled who gets what memory, at what price, and when. Until new wafer capacity comes online at scale — a process that cannot be accelerated past the mid-to-late 2027 horizon — consumers and enterprise buyers outside the AI supply chain will absorb that cost.

Frequently Asked Questions

Why is DDR5 RAM so expensive in 2026?

AI data centers require high-bandwidth memory (HBM), a specialized form of DRAM that consumes roughly three times the wafer capacity per gigabyte compared to standard DDR5. Samsung, SK Hynix, and Micron — which control over 95% of global DRAM production — have redirected manufacturing capacity toward HBM because it commands margins five to ten times higher than consumer memory, leaving the consumer DDR5 market chronically undersupplied.

Will DDR5 prices drop in 2026?

Meaningful price relief is not expected before the second half of 2027, when new manufacturing capacity from SK Hynix's M15X facility and Micron's Idaho fab begins coming online. Samsung's larger P5 megafab targets mass production only in late 2028. SK Hynix's chairman has publicly warned that the supply shortfall will exceed 20% through 2030, and SK Hynix's available capacity is currently described by industry sources as "essentially zero."

How does AI demand affect RAM prices for PC builders?

Each high-bandwidth memory module an AI accelerator requires consumes silicon wafer area that could otherwise produce approximately three to four standard DDR5 modules. As hyperscalers — including Microsoft, Google, Amazon, and Meta — continue expanding AI infrastructure, memory manufacturers prioritize filling those orders at premium prices, leaving less supply and higher spot prices for everyone else.

Is nbd-vram a real alternative to buying more DDR5?

For a specific set of Linux users — those with NVIDIA GeForce GPUs running workloads that keep VRAM partially idle, particularly on laptops with soldered memory — nbd-vram offers a functional way to use GPU VRAM as system swap space. It works by routing data through the NBD protocol over a Unix socket to the CUDA driver. The tool introduces PCIe bus latency overhead and competes with GPU workloads for VRAM, so it is not suitable as a substitute for actual DDR5 in latency-sensitive or GPU-intensive work.