Japan's Ministry of Economy, Trade and Industry announced Friday that the government has made an additional ¥150 billion ($960 million) equity investment in Rapidus — the state-backed chipmaker racing to produce 2-nanometer semiconductors by 2027 — marking the second direct equity injection into the company and deepening a governance arrangement that gives Tokyo veto power over key management decisions. The investment flows through the Information-technology Promotion Agency (IPA) and is earmarked for manufacturing equipment for 2nm mass production and research into the next-generation 1.4nm process. METI minister Ryosei Akazawa called Rapidus "a national undertaking that must succeed for the benefit of Japan."
Friday's announcement also laid out the full subsidy roadmap: an additional ¥631.5 billion in R&D funding for fiscal year 2026-27, and roughly ¥300 billion more in fiscal year 2027-28. Combined with prior investments, total projected government support is on track to exceed ¥3 trillion — roughly $18.8 billion — by the end of fiscal 2027, according to METI. The cumulative private-sector commitment stands at ¥167.6 billion from 32 companies, including Canon, Denso, Fujitsu, Kioxia, NTT, SoftBank, Sony, Toyota, and the Development Bank of Japan, per Rapidus's February 2026 announcement. Japan's total chip market share has fallen from roughly 50 percent in the late 1980s to approximately 10 percent today — the scale of the decline that this program is designed to reverse.
Japan Moves From Subsidies to Shareholders
What is new about this week's investment is its form, not its size. For most of Rapidus's existence, Tokyo channeled money through R&D grants administered by the New Energy and Industrial Technology Development Organization (NEDO) and other agencies — a model that kept the government at arm's length from the company's management. That changed with legislation enacted under Prime Minister Sanae Takaichi that cleared direct equity investment for the first time.
In February 2026, Rapidus closed its first equity round: ¥267.6 billion, with ¥100 billion from the IPA and ¥167.6 billion from 32 private companies. The government received roughly 10 percent of voting shares from that round but structured the majority of its stake in non-voting convertible stock — a design that preserves the appearance of limited control while retaining the ability to convert to majority ownership if the company faces financial distress. Critically, the government also acquired a "golden share" granting veto rights over major corporate decisions. Friday's ¥150 billion injection raises total government equity to ¥250 billion.
The arrangement will deepen further. For fiscal years 2027 and 2028, Tokyo has decided to directly build factory buildings and manufacturing equipment with public funds and then transfer those assets to Rapidus as in-kind contributions in exchange for shares — a mechanism that would further increase the government's stake without requiring Rapidus to raise that capital independently on the private market.
How Rapidus Plans to Make 2nm Chips: Gate-All-Around Transistors and EUV Lithography
The technical underpinning of Rapidus's program is IBM's second-generation gate-all-around (GAA) nanosheet transistor architecture — a fundamental departure from the FinFET design that has driven the industry for over a decade. In a FinFET transistor, the gate electrode surrounds the channel on three sides, a structure that enabled scaling down to the 3nm generation but runs into increasing current-leakage problems at smaller dimensions. In a GAA nanosheet design, the gate completely surrounds the channel on all four sides, using stacked flat silicon sheets as the current-carrying medium. IBM's 2nm prototype, which Rapidus is commercializing, uses a three-layer silicon nanosheet stack. The design promises 45 percent better performance or 75 percent lower power consumption compared to 7nm chips, according to IBM's 2021 benchmark data.
Patterning the circuit features for a GAA 2nm chip requires Extreme Ultraviolet (EUV) lithography — a technology that exposes silicon wafers using light at a wavelength of 13.5 nanometers, far shorter than the 193nm deep-UV tools that defined prior generations. ASML, the Dutch equipment manufacturer that is the world's sole producer of high-numerical-aperture EUV machines, delivered Rapidus's first EUV system to the IIM-1 foundry in Chitose, Hokkaido, in December 2024 — the first EUV tool ever installed in Japan for mass-production use. By April 1, 2025, Rapidus engineers had completed their first successful EUV exposure, approximately three months after the equipment arrived. CEO Atsuyoshi Koike has said no company in the world had previously achieved a functional EUV exposure in that timeframe after delivery. On July 18, 2025, Rapidus unveiled the resulting wafer: a working 2nm GAA transistor prototype whose devices had reached their target electrical characteristics.
A second distinctive technical choice is single-wafer processing. Conventional semiconductor fabs process many wafers simultaneously in large batches, amortizing equipment time across high volumes but creating long queues and cycle times of roughly 120 days from order to delivery. Rapidus processes each wafer individually. Per-unit cost is higher and per-tool throughput is lower, but the design compresses cycle times to approximately 50 days for standard runs and as little as 15 days for priority orders — a feature the company calls its short turnaround time (short-TAT) model. Rapidus released its Process Design Kit (PDK) in early 2026, a package of design rules, models, and circuit libraries that chip designers require to lay out chips compatible with a specific foundry process. PDK availability signals that Rapidus is now accepting design-in work from potential customers, of whom CEO Koike says more than 60 are in active discussions. Fujitsu, a founding private investor, is the confirmed first anchor commercial client.
What the Pilot Line Has Done — and What It Has Not Yet Proved
Analysts watching Rapidus closely draw a sharp distinction between prototype achievement and production readiness. Semiecosystem analyst Mark LaPedus wrote in April 2026 that he estimates a 5 percent probability that Rapidus will reach high-volume production by 2027, a 25 to 30 percent chance it will achieve pilot-line production in that timeframe, and a 65 to 70 percent likelihood that the company will still be in R&D mode when the target year arrives. The Center for Strategic and International Studies has noted that Rapidus has no track record in advanced manufacturing and that its reliance on IBM's technology transfer puts it in a different position from TSMC and Samsung, which have accumulated decades of iterative process knowledge in-house. Omdia Principal Analyst Manoj Sukumaran told The Register in February 2026 that Rapidus is unlikely to become a serious competitor to TSMC "all of a sudden."
The structural challenge is the gap between funding committed and funding required. The ASEAN+3 Macroeconomic Research Office has estimated that stable, full-scale 2nm production would require roughly ¥5 trillion — and some analysts cite ¥7 trillion or more. Japan's projected ¥3 trillion in total government support by end of fiscal 2027, while historically large for a single company, still leaves a significant gap. Japan's three megabanks are reportedly considering staged loans of up to ¥2 trillion, contingent on government guarantees, but no agreements have been finalized as of Friday.
TSMC and Samsung both moved into 2nm volume production in late 2025, putting Rapidus roughly two years behind those established foundries when its own mass-production line opens — assuming it opens on schedule.
How Does Japan's Chip Bet Compare to TSMC and Samsung?
Rapidus is not attempting to compete with TSMC on volume. The company's published target for IIM-1 is 25,000 wafer starts per month once the line is fully ramped — compared to TSMC's capacity measured in hundreds of thousands of wafer starts per month across its global network. The strategic logic is different: Rapidus is positioning itself as a geopolitically independent alternative source for leading-edge logic, a supply-chain diversification option for chip designers who do not want 100 percent of their advanced silicon flowing through Taiwan. For Japan, Rapidus also anchors a broader ecosystem play — NEDO has separately funded Fujitsu and IBM Japan to design chips specifically targeting Rapidus's process, with the goal of seeding domestic demand for its future products.
The roadmap extends beyond 2027. Rapidus plans a second Hokkaido fab targeting 1.4nm chips, with construction to begin in fiscal 2027 and production aimed for fiscal 2029. That timeline would, if met, put Rapidus within range of the generation after TSMC's current leading-edge node — a position that would represent a dramatic compression of the two-decade gap the company currently faces. A target IPO is planned around fiscal 2031.
Frequently Asked Questions
When will Rapidus start making 2nm chips?
Rapidus is targeting the start of 2nm mass production in fiscal year 2027, which runs from April 2027 to March 2028. The company is currently in the pilot-production phase at its IIM-1 foundry in Chitose, Hokkaido, where it has already produced working 2nm gate-all-around transistor prototypes and released its Process Design Kit to attract customers.
What is the golden share Japan holds in Rapidus?
A golden share is a special class of share that grants its holder veto power over major corporate decisions, regardless of how small the overall ownership stake is. Japan's government acquired a golden share in Rapidus as part of its February 2026 equity investment, giving METI the ability to block strategic decisions — such as a sale of the company or a change in its core mission — while allowing Rapidus to operate as a nominally private enterprise day to day.
Will Rapidus succeed in making 2nm chips by 2027?
Industry analysts are skeptical. Semiecosystem analyst Mark LaPedus estimated in April 2026 a 5 percent probability of high-volume production by 2027, with a 65 to 70 percent chance the company is still in R&D at that point. Rapidus has no prior track record in advanced chip manufacturing, and the funding committed remains below independent estimates of what full-scale production requires.
How does gate-all-around technology differ from previous chip designs?
Gate-all-around (GAA) transistors surround the current-carrying channel on all four sides with the gate electrode, rather than on three sides as in the FinFET architecture that dominated chips down to the 3nm generation. The extra contact improves electrostatic control, reduces current leakage at very small dimensions, and enables higher transistor density — properties that make GAA the foundational architecture for 2nm and smaller process nodes.
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