SK hynix has been quietly briefing key equipment and materials suppliers on a plan to nearly double its monthly DRAM wafer capacity — from approximately 550,000 wafers today to roughly 1 million by 2030 and 2031 — according to industry sources cited by The Elec, a South Korean semiconductor trade publication that first reported the details on June 5. The briefings, which have run for the past two months through SK hynix's purchasing teams and officials overseeing the Yongin semiconductor cluster, put specific production figures and phase schedules on the table for the first time, going well beyond the public pledge Chairman Chey Tae-won made at Computex 2026 four days ago.
The roadmap was already in motion when Nvidia CEO Jensen Huang walked up to the SK hynix booth at Computex 2026 on June 2 and wrote "Please Make More" on an HBM4E wafer — a gesture that became a widely circulated symbol of how acute the AI memory shortage has become. The supplier briefings reveal that Huang's appeal was answered before he made it.
Yongin's Six-Phase Cleanroom Architecture
The centerpiece of the plan is the Yongin semiconductor cluster, located south of Seoul and part of a multi-trillion-won manufacturing build-out spanning roughly 120 trillion won — among the largest semiconductor manufacturing investments in the world. The first Yongin fab is divided into six cleanrooms, and the company has moved forward the start of equipment installation for the first cleanroom to February 2027, pulling ahead from an earlier target of May 2027.
The production plan calls for each cleanroom to add 60,000 monthly wafer starts, with each successive phase beginning six months after the previous one reaches operational status. Under that schedule, the first Yongin fab alone reaches full capacity of 360,000 wafers per month by the first half of 2030 — six phases, six months apart, each contributing an equal increment of output.
That cadence carries a structural vulnerability. Industry participants quoted by The Elec noted that a single delayed equipment type could stall an entire phase. ASML, Lam Research, and Tokyo Electron Korea are among the global suppliers that have relocated or are in the process of relocating operations to the Yongin cluster to support the ramp — but even their proximity cannot eliminate the scheduling risk that one delayed machine creates for a timeline designed with no slack between phases.
Why HBM Wafer Production Consumes Three Times More Capacity
The scale of the Yongin build becomes easier to understand once the economics of high-bandwidth memory production are clear. High-bandwidth memory is a three-dimensional stack of DRAM dies connected vertically through through-silicon vias — microscopic copper pathways etched through each silicon layer — and bonded alongside a GPU or AI accelerator on a silicon interposer. That architecture requires nearly 20 incremental manufacturing steps beyond those needed for standard DRAM production, including TSV etching, wafer thinning, and multi-die stacking.
The manufacturing consequence is significant: each gigabyte of HBM consumes approximately three times the wafer capacity required for an equivalent gigabyte of standard DDR5 DRAM, according to Tom's Hardware analysis. The tools and equipment lines required for TSV processing and multi-die stacking cannot be repurposed for conventional DRAM without extensive re-tooling — meaning HBM capacity and standard DRAM capacity are not interchangeable.
SK hynix currently allocates roughly 30 percent of its DRAM wafer capacity to HBM production, a figure that industry analysts expect to approach 40 percent by 2027 as AI accelerator demand intensifies. Every wafer pushed into HBM is a wafer that no longer yields the commodity DDR5 and LPDDR memory used in phones and laptops — one reason DRAM prices for consumers have formed a persistent floor in the market.
M15X Cheongju Adds Near-Term Volume Before Yongin Arrives
Because Yongin's first cleanroom does not accept equipment until February 2027, near-term supply relief runs through the M15X fab in Cheongju. The facility is scheduled to begin operations in the second half of 2026 at an initial capacity of 40,000 wafers per month, reaching approximately 80,000 wafers per month in 2027. Combined with the 360,000 wafers per month that Yongin contributes by 2030, the two facilities push SK hynix's total DRAM wafer input toward 1 million per month between 2030 and 2031.
All of the new capacity being added at both Yongin and M15X is designated for DRAM production. For NAND flash memory, SK hynix intends to pursue higher layer counts — moving from its current 238-layer and 321-layer processes to future-generation stacking — rather than adding new wafer starts. The strategic logic is direct: DRAM, and particularly HBM, commands margins far above NAND, while the capital cost of new DRAM cleanrooms is justified by a demand trajectory that Chey has described as extending to 2030 at minimum.
How Far the Plan Was Ahead of the Optics
One detail in The Elec's reporting reframes the Huang moment at Computex. The supplier briefings began approximately two months ago — meaning SK hynix's purchasing teams were already circulating specific production targets with equipment partners well before the June 2 public announcement and the image of Huang writing on the wafer. The plan was not a reaction to a buyer's symbolic request. It preceded it.
SK hynix had held a notably reluctant position on new capacity as recently as March 2026, when Chey told reporters at Nvidia's GPU Technology Conference in San Jose that adding new capacity was "not something we planned." That statement came despite his own warning at the same event that the memory shortage would persist until 2030. The reversal between March and June — from publicly declining new capacity to privately briefing suppliers on a near-doubling plan — reflects both the persistence of demand signals and reports that some Nvidia-adjacent customers had offered to purchase SK hynix's own EUV lithography tools and prefund production lines to accelerate supply.
SK hynix held a 58 percent share of the global high-bandwidth memory market in the first quarter of 2026, according to Counterpoint Research, with Samsung Electronics and Micron Technology each holding approximately 21 percent. Its entire 2026 HBM production is sold out.
Wuxi Capacity Faces US Export Control Ceiling
Not all of SK hynix's current 550,000 monthly wafer starts are equally expandable. Approximately 200,000 of those wafers — roughly 36 percent of the total — are produced at its Wuxi fab in Jiangsu Province, China. US Commerce Department rules that took effect at the end of 2025 prohibit Samsung and SK hynix from receiving equipment needed to expand or upgrade their China-based DRAM fabs. The Wuxi plant cannot, under current regulations, add new process nodes or add wafer starts.
This creates a structural constraint on the 1 million wafer target: every wafer in that figure counted as coming from Wuxi represents capacity that cannot grow. Reaching 1 million monthly wafers by 2030 therefore depends almost entirely on the Yongin and Cheongju fabs delivering on schedule. The same export control regime that freezes Wuxi is what drives the investment urgency at Yongin.
Suppliers Cautious After 2022 Whiplash
Some of SK hynix's major equipment and materials partners are watching this plan with more caution than the headline figures might suggest. In 2022, SK hynix shared capital expenditure guidance with suppliers for the following year, then sharply reduced equipment orders that autumn — a reversal that forced suppliers who had already purchased components based on the earlier guidance to absorb significant cash flow losses, according to The Elec's sourcing.
The six-month-per-cleanroom ramp cadence that defines the Yongin plan is operationally tight. Equipment suppliers have noted that even a single delayed delivery could cascade through the schedule, because each phase assumes the prior phase has reached operational status before the next begins. One partner-company official told The Elec that near-term investment growth is certain and broadly positive for equipment and materials suppliers, but said the full roadmap is contingent on memory demand holding.
What distinguishes this round of guidance from 2022, in the view of some industry participants, is the source. The broader Yongin doubling thesis was articulated publicly by SK Group Chairman Chey himself at Computex — not by mid-level purchasing teams in private meetings alone. His separate remark at Computex, that sudden price spikes would harm the long-term health of the AI memory ecosystem, is being read by some suppliers as a signal that Yongin's build-out is a strategic priority the group will fund through a demand cycle rather than defer at the first sign of demand softness.
How Does HBM Production Differ From Standard DRAM Manufacturing?
High-bandwidth memory starts on the same front-end process as conventional DRAM — silicon wafers exposed to photolithography, etching, and deposition steps that define the memory cell array. SK hynix uses extreme ultraviolet lithography for its current 1a-nanometer DRAM process node, which the company also uses as the base die for HBM products. After the front-end steps are complete, HBM diverges sharply.
Production requires TSV formation: deep trenches are etched through the silicon substrate, lined with insulating material, and filled with copper to create vertical electrical pathways that will eventually connect each die in the finished stack. After TSV formation, wafers are thinned to between 50 and 100 microns — a mechanical step with no equivalent in standard DRAM production — reducing the height of each die before stacking. Dies are then tested, sorted, and stacked in configurations of eight or twelve layers for current-generation HBM3E, or up to sixteen layers for HBM4 products, with the stack bonded to a base logic die that handles addressing and signal routing. The completed stack is then attached to a silicon interposer alongside the GPU or AI accelerator it will serve.
The result is a finished module with a bit density roughly half that of equivalent-area standard DRAM — the TSV structures consume silicon area that would otherwise hold memory cells — but with data transfer rates measured in terabytes per second. That is why a cleanroom producing 60,000 HBM-destined wafers per month delivers far fewer bits per wafer than the same cleanroom producing DDR5, while consuming the same floorspace, toolset, and technician hours. It is also why doubling wafer starts does not double available memory output when an increasing fraction of those starts flow toward HBM.
Frequently Asked Questions
Why does HBM require so much more wafer capacity than standard DRAM?
High-bandwidth memory production requires nearly 20 additional manufacturing steps beyond standard DRAM, including through-silicon via etching, wafer thinning, and multi-die stacking. These steps both consume additional cleanroom time per wafer and produce dies with lower bit density than standard DRAM, because TSV structures occupy silicon area that would otherwise hold memory cells. The result is that each gigabyte of HBM consumes approximately three times the wafer capacity needed for an equivalent gigabyte of DDR5.
What is the Yongin semiconductor cluster and when will it come online?
The Yongin semiconductor cluster is a multi-fab manufacturing complex south of Seoul backed by approximately 120 trillion won in total investment. SK hynix's first Yongin fab is divided into six cleanrooms, with equipment installation for the first phase scheduled to begin in February 2027. Each phase adds 60,000 monthly wafer starts every six months, with the first Yongin fab reaching its full 360,000-wafer-per-month contribution by the first half of 2030.
When will the AI memory shortage end?
SK Group Chairman Chey Tae-won has repeatedly forecast that the structural memory shortage driven by AI demand will persist until at least 2030. Analysts at Gartner have indicated that meaningful price relief is unlikely before late 2027, and wafer supply is running more than 20 percent below demand, according to figures Chey cited at Computex 2026. Even SK hynix's 1 million wafer target, if achieved on schedule, may not proportionally increase available HBM output given the wafer capacity each HBM gigabyte consumes.
What happens to the SK hynix expansion plan if DRAM demand softens?
Supplier caution stems partly from a 2022 precedent in which SK hynix gave partners capex guidance for the following year and then sharply reduced equipment orders that autumn, causing cash flow losses for suppliers who had already purchased components. The six-month-per-cleanroom cadence at Yongin leaves little scheduling slack: a single delayed equipment delivery could cascade through the ramp schedule. Chairman Chey's public commitment at Computex and his remarks on price stability are being read by some in the industry as a signal that the Yongin plan will be funded through demand fluctuations, but the historical record is present in every supplier's planning.
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