Intel brought its most complex chiplet design ever to Computex 2026 in Taipei on Tuesday, formally launching the Xeon 6+ "Clearwater Forest" processor family — the company's first data center CPU with compute tiles built on its 18A process node. The flagship Xeon 6990E+ packs 288 Darkmont efficiency cores into a single socket and is available immediately through Dell Technologies, Hewlett Packard Enterprise, Lenovo, and Supermicro.
The launch is Intel's most concrete evidence yet that 18A is no longer a roadmap promise. After years of manufacturing setbacks and a widely watched turnaround under CEO Lip-Bu Tan, the company now has enterprise hardware built on its most advanced node shipping through tier-one server vendors on the same day it was announced.
Intel 18A Process Node Debuts in Production Data Center Silicon
Clearwater Forest is one of Intel's most architecturally intricate designs. The 6990E+ stacks 12 compute tiles fabricated on Intel's 18A node — each carrying 24 Darkmont E-cores — atop three active base tiles built on Intel 3, which house the L3 cache and memory controllers. Two I/O tiles built on Intel 7 complete the stack. Intel's Foveros Direct 3D packaging bonds the stacked layers vertically, while 12 EMIB bridges link tiles horizontally in a 2.5D arrangement.
The result is a chip with 576 MB of shared L3 cache — more than five times the 108 MB ceiling of the prior Sierra Forest generation — alongside support for 12 channels of DDR5-8000 memory and 96 PCIe Gen 5 lanes on the LGA 7529 socket. The 6990E+ ships in two power configurations — 450 watts and 330 watts — with the lower-TDP variant trading some clock headroom for efficiency in density-constrained deployments.
One significant constraint: the Darkmont E-cores run a single thread per core and cap out at AVX2 instruction support. AVX-512 — required for certain high-performance computing and AI inference workloads — is absent, a deliberate tradeoff Intel made to prioritize core density over per-core complexity. For data centers running cloud-native, throughput-oriented workloads at scale, Intel argues the 288-core density advantage compensates. Existing Xeon 6 platform operators can upgrade with a BIOS update, as Clearwater Forest is compatible with the same LGA 7529 socket used by Granite Rapids-AP deployments already in the field.
288-Core Xeon Outperforms AMD EPYC Per Thread, But Not Per Die
Intel's competitive claims at Computex deserve careful framing. The company says the 6990E+ delivers 30% higher average performance per thread than AMD's 192-core EPYC 9965 "Turin" processor, and 55% better performance per watt compared to its own prior-generation Xeon 6780E flagship.
The per-thread framing matters. AMD's EPYC 9965 uses simultaneous multi-threading, effectively offering two logical threads per physical core; Intel's Clearwater Forest does not. A per-thread advantage does not automatically translate into a full-die throughput lead, and Intel did not publish total-throughput comparisons against AMD. Tom's Hardware senior CPU analyst Jake Roach noted the omission directly in the publication's Computex coverage, observing that Intel "doesn't have any data comparing average performance across the entire die to AMD's offerings" — a gap that independent benchmark labs will fill as review units reach them.
Generationally, the gap over Intel's own prior silicon is less ambiguous. Against the Xeon 6780E — the 144-core Sierra Forest flagship — Intel claims 2.26x higher average throughput and 55% better average performance per watt. At 40% CPU utilization, the 6990E+ also appears to maintain an efficiency advantage over the EPYC 9965, though Intel has not published the underlying workload methodology for that specific comparison.
Agentic AI Workloads Created a CPU Shortage No One Planned For
The timing of the Clearwater Forest launch lands in an unusual market moment. At a press roundtable Tuesday in Taipei, Tim Wilson, Intel's vice president and general manager of data center silicon engineering, described how the rise of agentic AI — software frameworks that decompose complex tasks across dozens or hundreds of parallel agents — has exposed a structural CPU gap in data centers built around GPU-first architectures.
"Data centers that have built on GPUs for the last three years are suddenly finding they're bottlenecked by the CPU," Wilson said during the Computex 2026 roundtable. "They have a massive GPU fleet that costs billions of dollars sitting idle, waiting for the CPU to respond." Intel's own customer conversations put typical GPU utilization in agentic deployments at roughly 20 to 30 percent — not because the GPUs are insufficient, but because the CPU orchestration layer cannot keep pace with the parallelism these workloads demand.
Clearwater Forest's 288-core density is designed for exactly this kind of throughput-first orchestration work. Agentic AI frameworks — software systems that dispatch agents to search the web, run code, query APIs, and interact with databases — generate enormous volumes of CPU-bound parallel tasks. The Darkmont E-cores lack the specialized matrix math extensions found on Intel's P-core Xeons and on AMD's EPYC line, but for workloads where the bottleneck is task-level parallelism rather than per-core compute depth, core count matters more than AVX width.
Intel Application Energy Telemetry Measures Power by Workload
A new feature introduced with Clearwater Forest is Intel Application Energy Telemetry, or AET — a hardware-based system that gives data center operators per-application, per-workload visibility into energy consumption, down to the level of individual software threads when needed. Intel says AET uses hardware counters already present in the silicon to attribute power draw to specific containers, virtual machines, microservices, and applications, rather than reporting only aggregate system-level power.
The practical implication for cloud operators is billing precision: providers currently estimate per-customer energy costs rather than measuring them directly, and AET gives them the hardware foundation to charge for actual measured consumption. Intel confirmed that AET will extend to future Xeon generations, including Diamond Rapids.
Intel Crescent Island GPU Bets Capacity Over HBM Bandwidth
Alongside Clearwater Forest, Intel detailed its Crescent Island data center GPU — a forthcoming AI inference accelerator built on the Xe3P graphics architecture that also powers Intel's Panther Lake client processors. The chip targets the inference market specifically, at a moment when enterprises needing more inference capacity cannot readily obtain it because the High Bandwidth Memory supply chain powering Nvidia's accelerators is sold out through at least 2027.
Crescent Island's defining characteristic is its memory approach. Where Nvidia and AMD build their top data center accelerators around High Bandwidth Memory, Intel's reference design uses LPDDR5X — a consumer-grade memory technology that is cheaper, lower-power, and air-coolable within a 350-watt thermal envelope. The reference configuration ships with 160 GB of LPDDR5X, but Intel confirmed that board partners can configure cards with up to 480 GB — a capacity figure that exceeds competing HBM-based designs on a per-card basis. Based on a 640-bit bus running 10.7 Gbps LPDDR5X modules, the estimated memory bandwidth is approximately 684 GB/s — significantly lower than the multiple terabytes per second available on competing HBM3e designs.
Intel has not yet published throughput benchmarks for Crescent Island. That omission leaves the bandwidth trade-off unresolved: LPDDR5X capacity is compelling for inference workloads bottlenecked by model footprint, but bandwidth-sensitive workloads that need to stream large model weights rapidly may favor HBM-equipped alternatives. Intel is targeting customer sampling in the second half of 2026, with broader availability to follow. The company is positioning its oneAPI software stack as the development platform for Crescent Island deployments.
Diamond Rapids Roadmap Confirmed, Hyper-Threading Question Open
Intel used Computex to formally confirm that Xeon 7 "Diamond Rapids," its next-generation all-P-core server processor family, is on track for a 2027 launch on its refined 18A-P process node. Diamond Rapids will support PCIe 6.0 connectivity and double the memory bandwidth of the current Xeon 6 generation, with approximately 50% more cores than Granite Rapids — pointing to roughly 192 P-cores in the flagship configuration.
The 18A-P node itself is a meaningful upgrade over the base 18A used in Clearwater Forest. Intel has published technical details showing 18A-P delivers 9% higher performance at equivalent power — or 18% lower power at equivalent performance — along with 50% improved thermal conductivity compared to 18A.
Intel's roundtable participants deferred detailed Diamond Rapids questions, pointing to "fuller commentary roughly two months out" — timing that aligns with the Hot Chips conference in August. One key question left open is whether Diamond Rapids will restore hyper-threading. CEO Lip-Bu Tan has publicly acknowledged that removing simultaneous multi-threading from Intel's E-core Xeon line "put us at a competitive disadvantage," but Intel has not confirmed whether Diamond Rapids — the next P-core generation — will bring it back for its launch. The answer matters in particular for virtualized deployments, where per-thread software licensing makes thread count as financially consequential as core count.
Intel 18A Supply Constrained as Demand Outpaces Production
The Clearwater Forest launch comes with a supply caveat that prospective buyers should factor into procurement timelines. Kira Boyko, Intel's product line director for E-core Xeon, acknowledged during Tuesday's Computex roundtable that 18A chip allocation is being managed "daily, in some cases" — a level of granularity that signals very tight supply against strong demand. Tim Wilson confirmed the allocation decisions reflect a balancing act across multiple Intel product lines all drawing from the same 18A fab capacity.
Intel's Q1 2026 earnings provided some context for the intensity of that demand. The company reported $13.6 billion in total revenue for the quarter, up 7% year-over-year, with data center and AI segment revenue reaching $5.1 billion — a 22% year-over-year gain that beat Wall Street expectations by more than $700 million. Shares gained more than 16% in after-hours trading on the earnings report. Intel guided Q2 2026 revenue to a range of $13.8 billion to $14.8 billion.
How Does Clearwater Forest Compare to AMD EPYC Venice?
AMD is expected to respond with EPYC Venice — its sixth-generation Zen 6 server platform — later in 2026. Venice is confirmed to offer up to 256 cores on TSMC's 2nm process node, with memory bandwidth scaling to 1.6 TB/s per socket and a claimed 70% performance improvement over the current EPYC Turin generation. AMD has already entered production ramp for Venice in Taiwan, and AMD CEO Lisa Su confirmed on the company's Q1 2026 earnings call that the launch remains on schedule for this year.
The direct comparison will be meaningful when it arrives. Clearwater Forest's 288 E-cores without hyper-threading sit opposite Venice's 256 Zen 6 cores with simultaneous multi-threading — and Intel's claimed 30% per-thread advantage over the current EPYC 9965 may look different against a Zen 6 core that AMD claims delivers 70% higher performance than Zen 5.
For data center architects deciding now, Clearwater Forest is available immediately with known specifications and broad OEM support. Venice's arrival date and final specifications remain unconfirmed. The 18A supply constraint Intel acknowledged publicly could limit Clearwater Forest availability in the near term regardless of the demand it is generating. Buyers evaluating a refresh have a real choice to make: act now on a proven platform with a tight supply chain, or wait for a competitive response that may shift the calculus substantially.
Frequently Asked Questions
What is Intel Xeon 6 Plus Clearwater Forest?
Xeon 6+ Clearwater Forest is Intel's second-generation E-core-only server processor, launched at Computex 2026 in Taipei. It is Intel's first data center CPU with compute tiles built on the company's 18A process node, packing up to 288 Darkmont efficiency cores per socket with 576 MB of shared L3 cache. Systems are available immediately through Dell, HPE, Lenovo, and Supermicro.
How does Intel Xeon 6+ compare to AMD EPYC?
Intel claims the flagship Xeon 6990E+ delivers 30% higher performance per thread than AMD's 192-core EPYC 9965. That comparison is per-thread, not per-die: AMD's EPYC uses simultaneous multi-threading, so its 192-core chip offers 384 logical threads versus 288 on the Xeon 6990E+. Independent reviewers have not yet published full-die throughput comparisons. AMD's next-generation 256-core EPYC Venice is expected later in 2026.
What is the Intel 18A process node?
Intel 18A is Intel's most advanced manufacturing technology, using gate-all-around RibbonFET transistors and PowerVia backside power delivery. Clearwater Forest marks the first time 18A has been used to manufacture compute tiles for commercial data center CPUs. Supply of 18A silicon is currently constrained, with Intel managing allocations on a near-daily basis.
When does Intel Diamond Rapids launch?
Intel officially confirmed Diamond Rapids — the Xeon 7 series and its next P-core data center processor — for a 2027 launch on the refined 18A-P process node. Diamond Rapids will support PCIe 6.0 and double the memory bandwidth of the current Xeon 6 generation. Intel has not yet confirmed final core counts or whether hyper-threading will return with that launch.
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