NASA's Jet Propulsion Laboratory has confirmed that a next-generation radiation-hardened processor developed under its High Performance Spaceflight Computing (HPSC) project is now benchmarking at 500 times the performance of the chips currently running on active deep-space missions — including the James Webb Space Telescope and the Curiosity and Perseverance rovers on Mars — a result that surpasses the program's own design target by a factor of five and sets up a tight certification race with the 2028 Artemis IV crewed Moon landing. The findings were published by JPL on May 12, 2026.
The chip, designated the PIC64-HPSC and built by Microchip Technology Inc. of Chandler, Arizona, in a commercial partnership with JPL that began in 2022, is still in qualification testing — not flight-certified — and no specific mission has been confirmed as its debut vehicle. Certification must be completed by late 2026 for the chip to remain eligible for NASA's Artemis program, which is targeting a crewed lunar landing in early 2028.
The Chip Running Your Deep-Space Fleet Is Older Than Your First Smartphone
To understand why a 500x jump matters, it helps to know what NASA is flying today. The RAD750, manufactured by BAE Systems, has been the dominant spaceflight processor for nearly two decades. Released in 2001 and first flown in 2005, it runs at a maximum clock speed of 200 MHz — comparable to a mid-1990s desktop PC. More than 150 RAD750 units have been launched into space. The James Webb Space Telescope, launched in December 2021, runs a single RAD750 clocked at just 118 MHz. Both Mars rovers, Curiosity and Perseverance, rely on the same architecture.
The tradeoff is intentional. Every chip destined for deep space must survive conditions that would destroy consumer electronics within hours: high-energy particles from the Sun and interstellar space that can flip individual memory bits and send a spacecraft into emergency shutdown, temperature swings of hundreds of degrees between sunlit and shadowed phases, violent launch vibrations, and — critically — no possibility of a hardware repair from Earth. The engineering discipline required, known as radiation hardening, sacrifices raw performance for reliability across missions measured in decades. Even ARM, whose processor cores appear in billions of phones, notes that compared to standard technology, radiation hardening carries "a high cost of development" and "a negative impact on power, performance and area."
For decades, that performance sacrifice meant spacecraft sent most of their collected data home raw, to be processed on Earth — a round-trip that spans anywhere from 16 minutes for Mars to nearly 10 hours for Uranus. Science that requires a rapid decision — whether to extend an observation of an unexpected volcanic eruption on Io, or to begin capturing a transient water plume from Enceladus — had to wait. Often, the moment passed.
How JPL's Benchmark Broke the Program's Own Target
The HPSC project formally launched in 2021. After passing Critical Design Review in 2024 and reaching tape-out — the stage at which the final design was sent to the foundry for fabrication — in mid-2025, the first physical chips were manufactured later that year.
Testing at JPL began in February 2026 with a deliberate symbolic act: engineers sent an email through the new processor with the subject line "Hello Universe," a reference to the "hello world" programs used to verify that new computing environments are working. The gesture carried weight. It was the first functional confirmation that a chip designed from scratch to survive deep space, built on a modern open-source RISC-V architecture, could actually run.
"We are putting these new chips through the wringer by carrying out radiation, thermal, and shock tests while also evaluating their performance through a rigorous functional test campaign," said Jim Butler, High Performance Space Computing project manager at JPL.
The original design target was a 100-fold increase over current spaceflight processors. Early benchmarks have exceeded that substantially: JPL's official results show the chip operating at 500 times the performance of the radiation-hardened processors currently in use on active missions. Independent technical presentations at the 2025 Lunar and Planetary Science Conference, drawing on pre-release HPSC data, characterized the chip's scalar processing at roughly 100x the RAD750, with the 500x figure achieved under vector and AI workloads — the category of processing most relevant to autonomous decision-making. In practical terms, a 2025 NASA technical summary described HPSC performance as "roughly equivalent to an Intel i7 circa 2022 Windows laptop" — performance unavailable on any previous spaceflight processor.
"Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing," said Eugene Schwanbeck, program element manager in NASA's Game Changing Development program at NASA's Langley Research Center. "NASA's commitment to advancing spaceflight computing is a triumph of technical achievement and collaboration."
Full radiation, thermal, and shock testing is expected to conclude in the coming weeks. Every test conducted so far has passed.
What 500x Enables: Spacecraft That Decide Without Asking
The performance gain is not an end in itself. What it unlocks is qualitatively different from previous incremental improvements in spaceflight computing.
The HPSC is designed as a system-on-a-chip, integrating central processing units, vector processing units for AI workloads, advanced networking, memory, and input/output interfaces into a single compact package — a form factor common in smartphones, now brought to radiation-hardened spaceflight hardware for the first time. It is built on RISC-V, an open-source processor instruction set, which means existing flight software developed for other platforms can be ported without the vendor lock-in that has historically constrained NASA's computing ecosystem.
The practical consequence is onboard autonomy: a future probe approaching Europa or orbiting an active asteroid could detect an unexpected event, assess its scientific value, reconfigure its instruments, and begin capture — all without waiting for a command from a controller on Earth who will not receive the initial sensor reading for anywhere from 35 minutes to five hours, depending on where in the solar system the spacecraft is operating.
The chip is also expected to transform the economics of data return. Raw sensor data transmitted across billions of kilometers at the limited bandwidths available to deep-space missions represents an enormous bottleneck — one that forces scientists to make choices weeks in advance about what to observe and what to discard. An HPSC-equipped spacecraft could process, compress, and prioritize its findings before transmission, extracting more science from each bit sent back to Earth.
Samples of the chip have already been provided to early-access partners in the defense and commercial aerospace industry. Microchip Technology is separately developing a commercial derivative targeting aviation safety systems and autonomous vehicles — two sectors where the failure modes most resemble spaceflight: remote operation, hardware faults with catastrophic consequences, and no opportunity for human intervention in real time.
The Certification Race and the 2028 Moon Landing
The chip's fate is now tied to an aggressive schedule. Artemis IV, NASA's first planned crewed lunar landing since Apollo 17 in 1972, is targeting early 2028. For the HPSC to be incorporated into the computing architecture of that mission — or any Artemis mission — it must clear JPL certification by late 2026.
That deadline leaves roughly six months. Flight certification for any new spaceflight hardware is a multi-year process under normal conditions; the HPSC project has been compressing that timeline by running qualification testing in parallel with performance benchmarking, rather than in sequence. No outcome is guaranteed.
No specific mission has been designated as the HPSC's first flight. NASA's official language — that the chip will be incorporated into "Earth orbiters, rovers exploring planetary surfaces, crewed habitats, and deep space missions" once certified — describes an intention, not a commitment. The chip could fly on Artemis. It could also debut on a smaller robotic mission first.
A More Capable Spacecraft Meets an Unresolved Cybersecurity Problem
The HPSC's promise of onboard autonomy — a spacecraft that interprets sensor data and acts without human instruction — also raises a concern that the U.S. Government Accountability Office has been raising for years without resolution.
In a June 2025 report, GAO found that NASA had not fully implemented cybersecurity risk management for selected major projects, making 16 recommendations and finding that of seven required risk management steps, most were only partially fulfilled. NASA did not concur with five of those 16 recommendations. GAO stated that all 16 remain warranted.
A separate May 2024 GAO report found that NASA had failed to incorporate its own spacecraft security principles into acquisition policies and standards — the point in the process where security requirements are written into hardware and software contracts. As of May 2025, that recommendation had not been implemented.
GAO's assessment is direct: "A cyber incident could result in loss of mission data, decreased lifespan or capability of space systems, or the loss of control of space vehicles."
The implications are more significant as spacecraft become more capable. An autonomous spacecraft running on an AI-capable chip — one designed to recognize events, make decisions, and act without human input — represents a more complex attack surface than a passive data relay. If a vehicle can be commanded to ignore a safe-mode trigger, or directed to orient itself away from its communication antenna, the consequences are mission-ending and, in the case of crewed vehicles, potentially fatal. NASA's cybersecurity acquisition policies do not yet mandate the controls that would address these risks.
The threat is not hypothetical. In December 2025, security researchers at startup AISLE discovered that a three-year-old vulnerability in NASA's CryptoLib software — the library protecting communications between Earth and active spacecraft — had survived multiple human code reviews undetected. An automated AI analysis tool found and helped fix it in four days. AISLE described the flaw as one that could allow an attacker with access to operator credentials to "inject arbitrary commands that execute with full system privileges." NASA has not publicly addressed how HPSC-specific cybersecurity requirements will be incorporated into mission contracts before the chip reaches flight hardware.
A Certification Deadline, an Open Security Question, and 2028 on the Clock
The HPSC chip has, by every available measure, done what it was designed to do. It runs. It exceeds its design target. It has passed early stress tests. The question is not whether the chip is capable — it is whether the institutional infrastructure around it, from certification timelines to cybersecurity policy, is ready to match what the hardware can deliver.
If JPL certification concludes on schedule and the GAO's cybersecurity recommendations are addressed before the chip reaches a crewed mission, the HPSC represents a genuine architectural shift in what space exploration can accomplish. Missions to the outer solar system, currently starved for computing power and dependent on Earth for every decision, could operate with a degree of real-time intelligence that the RAD750 era never permitted.
The universe sent back a promising early reply. Whether NASA is ready to receive the full message — securely, on time, and on a mission that matters — will be answered before the end of 2026.
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